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| CY7C1484V25 CY7C1485V25 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM Features * * * * * * * * * * * * * * Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 167 MHz Registered inputs and outputs for pipelined operation Optimal for performance (double cycle deselect) Depth expansion without wait state 2.5V core power supply (VDD) 2.5V/1.8V IO supply (VDDQ) Fast clock-to-output times -- 3.0 ns (for 250-MHz device) Provide high performance 3-1-1-1 access rate User selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable CY7C1484V25, CY7C1485V25 available in JEDECstandard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan "ZZ" Sleep Mode option Functional Description[1] The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at the rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. This part supports byte write operations (see "Pin Definitions" on page 5 and "Truth Table" on page 8 for further details). Write cycles can be one to four bytes wide, as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1484V25/CY7C1485V25 operates from a +2.5V core power supply while all outputs operate with a +2.5V or a +1.8V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. * * Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA Note 1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05286 Rev. *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 24, 2007 [+] Feedback CY7C1484V25 CY7C1485V25 Logic Block Diagram - CY7C1484V25 (2M x 36) A 0,A1,A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK BURST LOGIC Q1 COUNTER AND CLR ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ c,DQP C BYTE WRITE REGISTER DQ B,DQP B BYTE WRITE REGISTER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER Q0 DQ D, DQP D BYTE WRITE DRIVER DQ c,DQP C BYTE WRITE DRIVER DQ B,DQP B BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BW C OUTPUT REGISTERS OUTPUT BUFFERS E BW B DQs DQP A DQP B DQP C DQP D BW A BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Logic Block Diagram - CY7C1485V25 (4M x 18) A 0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP A BYTE WRITE REGISTER ENABLE REGISTER DQ B , DQP B BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BW B OUTPUT REGISTERS OUTPUT BUFFERS E DQs, DQPA DQPB BW A BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05286 Rev. *H Page 2 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Pin Configurations 100-Pin TQFP Pinout A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1484V25 (2M X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1485V25 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 A A VSS VDD A A A A A A A A A MODE A A A A A1 A0 A A VSS VDD Document #: 38-05286 Rev. *H A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1484V25 (2M x 36) 1 A B C D E F G H J K L M N P R NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW VSS 8 ADSC OE 9 ADV ADSP VDDQ 10 A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A A CY7C1485V25 (4M x 18) 1 A B C D E F G H J K L M N P R NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS `VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP 10 A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A A Document #: 38-05286 Rev. *H Page 4 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Pin Definitions Pin Name A0, A1, A IO InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "sleep" Input, active HIGH. When asserted HIGH, places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the IO circuitry. BWA,BWB BWC,BWD GW BWE CLK CE1 CE2 CE3 OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous ZZ InputAsynchronous IOSynchronous DQs, DQPs VDD VSS VSSQ [2] Power Supply Ground IO Ground VDDQ IO Power Supply Power supply for the IO circuitry. Note 2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry. Document #: 38-05286 Rev. *H Page 5 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Pin Definitions (continued) Pin Name MODE IO InputStatic Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. TDO JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG Synchronous feature is not used, this pin should be disconnected. This pin is not available on TQFP packages. JTAG Serial Input Synchronous JTAG Serial Input Synchronous JTAG Clock - - Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and 1G densities. is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state; its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the OE signal controls the outputs. Consecutive single read cycles are supported. The CY7C1484V25/CY7C1485V25 is a double cycle deselect part. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tri-states immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses need two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the BWE and BWX signals control the write operation. The CY7C1484V25/CY7C1485V25 provides byte write capability that is described in the "Truth Table for Read/Write" on page 9. Asserting BWE with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Because the CY7C1484V25/CY7C1485V25 is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so tri-states the output drivers. As a safety precaution, DQ are automatically Page 6 of 26 TDI TMS TCK NC NC(144M, 288M, 576M, 1G) Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1484V25/CY7C1485V25 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the ADSP or ADSC. The ADV input controls address advancement through the burst sequence. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. GW overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data Document #: 38-05286 Rev. *H [+] Feedback CY7C1484V25 CY7C1485V25 tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses need a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism is provided to simplify the write operations. Because the CY7C1484V25/CY7C1485V25 is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so tri-states the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1484V25/CY7C1485V25 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 120 2tCYC Unit mA ns ns ns ns Document #: 38-05286 Rev. *H Page 7 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Truth Table The truth table for CY7C1484V25/CY7C1485V25 follows.[3, 4, 5, 6, 7] Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE OE CLK X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X DQ L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Tri-State Q D Q Q Q D D Q Q D D L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Notes 3. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05286 Rev. *H Page 8 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Truth Table for Read/Write The read/write truth table for CY7C1484V25 follows.[5, 8] Function (CY7C1484V25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Truth Table for Read/Write The read/write truth table for CY7C1485V25 follows.[5] Function (CY7C1485V25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes GW H H H H H BWE H L L L L BWB X H H L L BWA X H L H L Note 8. Table contains only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document #: 38-05286 Rev. *H Page 9 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1484V25/CY7C1485V25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V or 1.8V I/O logic levels. The CY7C1484V25/CY7C1485V25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Mode Select (TMS) The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TAP Controller Block Diagram 0 Bypass Register 210 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TM S TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05286 Rev. *H Page 10 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the "TAP Controller Block Diagram" on page 10. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary `01' pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register and the x18 configuration has a 54-bit-long register. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables on page 14 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in "Identification Register Definitions" on page 13. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in "Identification Codes" on page 14. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of Document #: 38-05286 Rev. *H SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the ShiftIR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction, which is to be executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, but the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). Page 11 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK ) t TM SS 2 3 4 5 6 t TH t TM SH t TL t CY C Test M ode Select (TM S) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON'T CA RE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 20 20 10 50 20 ns MHz ns ns ns ns Description Min Max Unit Output Times Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document #: 38-05286 Rev. *H Page 12 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 2.5V TAP AC Test Conditions Input pulse levels .................................................VSS to 2.5V Input rise and fall time..................................................... 1 ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V 1.8V TAP AC Test Conditions Input pulse levels..................................... 0.2V to VDDQ - 0.2 Input rise and fall time .....................................................1 ns Input timing reference levels............................................. .9V Output reference levels .................................................. 0.9V Test load termination supply voltage .............................. 0.9V 2.5V TAP AC Output Load Equivalent 1.25V 50 TDO Z O= 50 20pF 1.8V TAP AC Output Load Equivalent 0.9V 50 TDO Z O= 50 20pF TAP DC Electrical Characteristics And Operating Conditions (0C < TA < +70C; VDD = 2.5V 0.125V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND VI VDDQ IOH = -1.0 mA IOH = -100 A IOL = 1.0 mA IOL = 100 A Test Conditions VDDQ = 2.5V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V VDDQ = 2.5V VDDQ = 1.8V 1.7 1.26 -0.3 -0.3 -5 Min. 1.7 2.1 1.6 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.36 5 Max. Unit V V V V V V V V V V A Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1484V25 (2M x 36) 000 01011 000110 100100 00000110100 1 CY7C1485V25 (4M x 18) 000 01011 000110 010100 00000110100 1 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Enables unique identification of SRAM vendor Indicates the presence of an ID register Note 11. All voltages refer to VSS (GND). Document #: 38-05286 Rev. *H Page 13 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order -165BGA Bit Size (x36) 3 1 32 73 Bit Size(x18) 3 1 32 54 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/ PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures IO ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Description Boundary Scan Exit Order (2M x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 165-Ball ID R3 P2 R4 P6 R6 N6 P11 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 165-Ball ID L10 K11 J11 K10 J10 H11 G11 F11 E11 D10 D11 C11 G10 F10 E10 A10 B10 A9 B9 A8 Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 165-Ball ID B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 Document #: 38-05286 Rev. *H Page 14 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Boundary Scan Exit Order (4M x 18) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 R4 P6 R6 N6 P11 Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 165-Ball ID R8 P3 P4 P8 P9 P10 R9 R10 R11 M10 L10 K10 J10 H11 G11 F11 E11 D11 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 165-Ball ID C11 A11 A10 B10 A9 B9 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2 Document #: 38-05286 Rev. *H Page 15 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +3.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD VDDQ 2.5V -5%/+5% 1.7V to VDD Electrical Characteristics Over the Operating Range[12, 13] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12] For 2.5V IO For 1.8V IO For 2.5V IO, IOH = -1.0 mA For 1.8V IO, IOH = -100 A For 2.5V IO, IOL = 1.0 mA For 1.8V IO, IOL = 100 A For 2.5V IO For 1.8V IO For 2.5V IO For 1.8V IO Input Leakage Current except ZZ and MODE GND VI VDDQ 1.7 1.26 -0.3 -0.3 -5 -30 5 -5 30 -5 5 450 450 400 200 200 200 120 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power Down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz Test Conditions Min. 2.375 2.375 1.7 2.0 1.6 0.4 0.2 VDD + 0.3V VDD + 0.3V 0.7 0.36 5 Max. 2.625 VDD 1.9 Unit V V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB2 ISB3 Automatic CE VDD = Max, Device Deselected, All speeds Power Down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CE VDD = Max, Device Deselected, 4.0-ns cycle, 250 MHz Power Down or VIN 0.3V or VIN > VDDQ - 0.3V 5.0-ns cycle, 200 MHz Current--CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz Automatic CE Power Down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 All Speeds 200 200 200 135 mA mA mA mA ISB4 Notes 12. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) >-2V (pulse width less than tCYC/2). 13. Power up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05286 Rev. *H Page 16 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter CADDRESS CDATA CCTRL CCLK CI/O Description Address Input Capacitance Data Input Capacitance Control Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V 100 TQFP Package 6 5 8 6 5 165 FBGA Package 6 5 8 6 5 Unit pF pF pF pF pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 24.63 2.28 165 FBGA Package 16.3 2.1 Unit C/W C/W AC Test Loads and Waveforms 2.5V IO Test Load OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 R = 1667 VDDQ 5 pF GND R = 1583 10% ALL INPUT PULSES 90% 90% 10% 1 ns VL = 1.25V 1 ns (a) 1.8V IO Test Load OUTPUT Z0 = 50 1.8V INCLUDING JIG AND SCOPE (b) (c) R = 14K VDDQ - 0.2 5 pF 0.2 R = 14 K 10% 1 ns ALL INPUT PULSES 90% 90% 10% 1 ns OUTPUT RL = 50 VL = 0.9V (a) INCLUDING JIG AND SCOPE (b) (c) Document #: 38-05286 Rev. *H Page 17 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Switching Characteristics Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V and is 0.9V when VDDQ = 1.8V. Test conditions shown in (a) of "AC Test Loads and Waveforms" on page 17 unless otherwise noted. Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSC, ADSP Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWX Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[15, 16, 17] Clock to High-Z[15, 16, 17] 0 3.0 OE LOW to Output Valid OE LOW to Output Low-Z[15, 16, 17] OE HIGH to Output High-Z[15, 16, 17] 1.3 1.3 3.0 3.0 0 3.0 3.0 1.3 1.3 3.0 3.0 0 3.4 3.0 1.5 1.5 3.4 3.4 3.4 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 4.0 2.0 2.0 5 2.0 2.0 6 2.2 2.2 ns ns ns Description VDD(Typical) to the First Access[14] 250 MHz Min 1 Max 200 MHz Min 1 Max 167 MHz Min 1 Max Unit ms Notes 14. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of "AC Test Loads and Waveforms" on page 17. Transition is measured 200 mV from steady-state voltage. 16. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 17. This parameter is sampled and not 100% tested. Document #: 38-05286 Rev. *H Page 18 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Switching Waveforms Figure 1 shows read cycle timing waveforms.[18] Figure 1. Read Cycle Timing tCYC CLK tCH t ADS tADH tCL ADSP t ADS tADH ADSC t AS tAH ADDRESS A1 t WES tWEH A2 A3 Burst continued with new base address GW, BWE,BW X t CES tCEH Deselect cycle CE t ADVS tADVH ADV ADV suspends burst OE t OEV t CLZ t OEHZ t OELZ t CO t DOH t CHZ Data Out (DQ) High-Z Q(A1) t CO Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) Single READ BURST READ Burst wraps around to its initial state DON'T CARE UNDEFINED Note 18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document #: 38-05286 Rev. *H Page 19 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Switching Waveforms (continued) Figure 2 shows write cycle timing waveforms. [18, 19] Figure 2. Write Cycle Timing t CYC CLK tCH t ADS tADH tCL ADSP t ADS tADH ADSC extends burst t ADS tADH ADSC t AS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 t WES tWEH BWE, BWX t WES tWEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t DS t DH Data in (D) High-Z t OEHZ D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE DON'T CARE BURST WRITE UNDEFINED Extended BURST WRITE Note 19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW. Document #: 38-05286 Rev. *H Page 20 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Switching Waveforms (continued) Figure 3 shows read/write cycle timing waveforms.[18, 20, 21] Figure 3. Read/Write Cycle Timing t CYC CLK tCH t ADS tADH tCL ADSP ADSC t AS tAH ADDRESS BWE, BW X A1 A2 A3 t WES tWEH A4 A5 A6 t CES tCEH CE ADV OE tCO t DS tDH t OELZ Data In (D) Data Out (Q) High-Z tCLZ tOEHZ D(A3) D(A5) D(A6) High-Z Q(A1) Back-to-Back READs Q(A2) Single WRITE DON'T CARE Q(A4) Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 20. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Document #: 38-05286 Rev. *H Page 21 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Switching Waveforms (continued) Figure 4 shows ZZ mode timing waveforms.[22, 23] Figure 4. ZZ Mode Timing CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON'T CARE Notes 22. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05286 Rev. *H Page 22 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1484V25-167AXC CY7C1485V25-167AXC CY7C1484V25-167BZC CY7C1485V25-167BZC CY7C1484V25-167BZXC CY7C1485V25-167BZXC CY7C1484V25-167AXI CY7C1485V25-167AXI CY7C1484V25-167BZI CY7C1485V25-167BZI CY7C1484V25-167BZXI CY7C1485V25-167BZXI 200 CY7C1484V25-200AXC CY7C1485V25-200AXC CY7C1484V25-200BZC CY7C1485V25-200BZC CY7C1484V25-200BZXC CY7C1485V25-200BZXC CY7C1484V25-200AXI CY7C1485V25-200AXI CY7C1484V25-200BZI CY7C1485V25-200BZI CY7C1484V25-200BZXI CY7C1485V25-200BZXI 250 CY7C1484V25-250AXC CY7C1485V25-250AXC CY7C1484V25-250BZC CY7C1485V25-250BZC CY7C1484V25-250BZXC CY7C1485V25-250BZXC CY7C1484V25-250AXI CY7C1485V25-250AXI CY7C1484V25-250BZI CY7C1485V25-250BZI CY7C1484V25-250BZXI CY7C1485V25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Document #: 38-05286 Rev. *H Page 23 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.000.20 14.000.10 100 1 81 80 1.400.05 0.300.08 22.000.20 20.000.10 0.65 TYP. 30 31 50 51 121 (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX. NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0-7 R 0.08 MIN. 0.20 MAX. 0.600.15 0.20 MIN. 1.00 REF. DETAIL 51-85050-*B A Document #: 38-05286 Rev. *H 0.10 R 0.08 MIN. 0.20 MAX. Page 24 of 26 [+] Feedback CY7C1484V25 CY7C1485V25 Package Diagrams (continued) Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B PIN 1 CORNER O0.450.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B A B D E F G 1.00 C C D E F G 17.000.10 H J K 14.00 H J K M N P R 7.00 L L M N P R A 5.00 10.00 0.530.05 0.25 C +0.05 -0.10 1.00 0.35 0.15 C B 0.15(4X) 15.000.10 SEATING PLANE C 0.36 1.40 MAX. 51-85165-*A i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05286 Rev. *H Page 25 of 26 (c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1484V25 CY7C1485V25 Document History Page Document Title: CY7C1484V25/CY7C1485V25 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM Document Number: 38-05286 REV. ** *A ECN NO. 114672 118285 Issue Date 08/21/02 01/20/03 Orig. of Change PKS HGK New Data Sheet Changed tCO from 2.4 to 2.6 ns for 250 MHz Updated Features on package offering Updated Ordering information Changed Advanced Information to Preliminary Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified "Functional Overview" section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250-MHz offering and included 225-MHz speed bin Changed package outline for 165FBGA package Removed 119-BGA package offering Removed 225-MHz offering and included 250-MHz speed bin Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin Changed JA from 16.8 to 24.63 C/W and JC from 3.3 to 2.28 C/W for 100 TQFP Package on Page # 16 Added lead-free information for 100-Pin TQFP and 165 FBGA Packages Added comment of `Lead-free BG packages availability' below the Ordering Information Changed typo in the part number from CY7C1484V33 and CY7C1485V33 to CY7C1484V25 and CY7C1485V25 respectively on page numbers 2, 3, 4 and 21 Unshaded 200 and 167 MHz speed bins in the AC/DC Table and Selection Guide Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Industrial Operating Range Modified VOL, VOH Test Conditions Updated Ordering Information Table Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed the description of IX from Input Load Current to Input Leakage Current on page# 16 Changed the IX current values of MODE on page # 16 from -5 A and 30 A to -30 A and 5 A Changed the IX current values of ZZ on page # 16 from -30 A and 5 A to -5 A and 30 A Changed VIH < VDD to VIH < VDD on page # 16 Replaced Package Name column with Package Diagram in the Ordering Information table Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. Description of Change *B 233368 See ECN NJY *C 299511 See ECN SYT *D 320197 See ECN PCI *E 331513 See ECN PCI *F 416221 See ECN RXU *G 472335 See ECN VKN *H 1062042 See ECN VKN/KKVTMP Added footnote #2 related to VSSQ Document #: 38-05286 Rev. *H Page 26 of 26 [+] Feedback |
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